The present invention relates to an analog-to-digital converting apparatus for converting an analog value into a digital value, and more particularly to an analog-to-digital converter required to operate at a low voltage or operate at a high speed.
Recently, semiconductor integrated circuits are used in all fields, and the demand for low power consumption is intensified as being represented by the applications in portable electronic appliances. For low power consumption, in the first place, it is necessary to lower the supply voltage.
In conventional analog circuits including A/D (analog to digital) converters, the analog switch as shown in FIG. 1A is used widely in order to handle an intermediate level voltage within a supply voltage range.
In the case of A/D converters, analog switches are used widely for the role as the switch for charging an input analog value in a sampling capacitor, the role as selector for taking out a comparative voltage from a built-in D/A converter in order to compare the sampled analog value with the reference comparative voltage, etc.
Generally, the analog switch is, in the case of CMOS process, composed by combining P-channel MOSFET and N-channel MOSFET in parallel so as to lower the ON resistance for the input in the supply voltage range.
However, if attempted to operate at a low voltage for lowering power consumption, in analog circuits and A/D converters widely using analog switches, it was very hard to guarantee the low voltage operation. This is because the transistor is not turned on in the relationship between the supply voltage and transistor threshold, transfer voltage.
That is, when the supply voltage is lowered (for example, from the ordinary voltage of 5.0, to 2.7V, 2.2V or the like), owing to the relationship between the MOSFET threshold V.sub.th (about 0.8V) and gate voltage Vgs, source voltage V.sub.bs (in this case, a voltage to be transferred, ranging from 0 to 2.7V, for example, an intermediate value of 1.35V), considering the N-channel MOS transistor, it follows that EQU V.sub.gs -V.sub.th -(V.sub.th increment by the portion of V.sub.th modulation due to V.sub.bs =about half of V.sub.bs) EQU =(2.7-1.35)-0.85-(1.35/2) EQU =-0.175V
and hence this MOS transistor cannot be turned on.
Since the N-channel MOS transistor is not turned on at the intermediate voltage of 1.35V, similarly, the P-channel MOS transistor is not turned on, and the intermediate voltage is not transferred normally (see FIG. 1B). In FIG. 1B, meanwhile, a.sub.1 denotes the ON resistance characteristic when boosted, a.sub.2 shows the ON resistance characteristic when not boosted, and a.sub.3 is the region where the ON resistance is excessive.
If attempted to operate at a high speed, elevation of ON resistance of analog switch causes the prolonging of the charging time to the sampling capacitor or the like. Accordingly, when operated at a high speed, the time necessary for charging is insufficient, and the precision is lowered as a result.
To solve such problems, transistors low in threshold V.sub.th may be used in part of the circuit. In this case, however, there is such a drawback that since the process is added, the cost is raised.
FIG. 2A is a diagram showing a general constitution of a boosting circuit, and FIG. 2B is a timing chart for explaining the operation of this circuit.
In FIG. 2A, a boosting circuit 2 is composed of switches SW1, SW2, and SW3, and capacitors C1 and C2. An output capacitor C3 is connected to the output side of the boosting circuit 2.
In the internal operation of the boosting circuit 2, charge period (t.sub.1) and charge pump period (t.sub.2) are repeated. In the charge period (t.sub.1), by changeover of switches SW1, SW2, SW3, corresponding signals .PHI.1, .PHI.2, .PHI.3 are delivered (ON). As a result, the capacitors C1 and C2 are connected parallel, and are individually charged at V.sub.dd.
On the other hand, in the charge pump period (t.sub.2), the switches SW1, SW2, SW3 are changed over, and corresponding signals .PHI.1', .PHI.2', .PHI.3' are delivered. As a result, the two capacitors C1 and C2 are connected in series, and the V.sub.dd potential charged in the capacitors C1 and C2 is doubled to be 2*V.sub.dd. Afterwards, a boosting voltage V.sub.cc (=2*V.sub.dd) is generated in the output capacitor C3.
The V.sub.dd potential charged in the capacitor C3 declines along with the operation of the A/D converter as its load, and gradually declines from 2*V.sub.dd. Accordingly, by repeating this operation, a boosting potential nearly equal to 2*V.sub.dd is always obtained.
However, the boosted V.sub.cc potential gradually declines as the electric charge is consumed in the process of charging and discharging operation of the circuit operating on the power source of the boosted potential V.sub.cc along with the converting action of the A/D converter. The potential lowered cannot be restored to the original level until transition to the next charge pump period.
Therefore, when the boosted potential is lowered more than a certain extent, due to such a fact that noise is superposed on the converting action of the A/D converter in the aspect of precision and operation speed, the A/D converter can be actually operated only for a shorter period than the clock period. In particular, in the case of the A/D converter incorporating a microcomputer it is required to stabilize the boosted voltage for a very long period for realizing various converting actions, such as scan operation for sequentially converting multiple analog input channels, repeat action for repeating conversion of same channel, and scan repeat action for repeating scan operation.
In addition, sudden changes of V.sub.cc potential generating at the timing of transition to the charge pump period have direct effects on the precision of the A/D converter, and hence it is not preferred to repeat boosting operation plural times within one conversion cycle.
Accordingly, for stabilization of the boosted potential for such a long period, there is no other effective means than accumulation of a sufficient electric charge in a huge stabilizing capacitor C3, which involves a problem of increase of cost in relation to the capacitor area.